/**
 *  jailhouse, a Linux-based partitioning hypervisor
 *
 * Copyright (C), 2022, Kylinsoft Corporation.
 *
 * @author mashuai01@kylinos.cn
 * @date 2023.03.27
 * @brief 
 * @note 
 */

#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
   
struct {
	struct  jailhouse_system header;
	__u64 cpus[1];
	struct  jailhouse_memory mem_regions[35];
	struct  jailhouse_irqchip irqchips[2];
	struct  jailhouse_pci_device pci_devices[0];
} __attribute__((packed)) config = {
	.header = {
		.signature =  JAILHOUSE_SYSTEM_SIGNATURE,
		.revision =  JAILHOUSE_CONFIG_REVISION,
		.flags =  JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
		.hypervisor_memory = {
			.phys_start = 0xa0000000,
			.size =       0x01000000,
		},
		.debug_console = {
			.address = 0x2800d000,
			.size = 0x1000,
			.type =  JAILHOUSE_CON_TYPE_PL011,
			.flags =  JAILHOUSE_CON_ACCESS_MMIO |
				  JAILHOUSE_CON_REGDIST_4,
		},   
		.platform_info = {
			.pci_mmconfig_base = 0x40000000,
			.pci_mmconfig_end_bus = 5,
			.pci_is_virtual = 0,
			.pci_domain = 1,

			.arm = {
				.gic_version = 3,
				.gicd_base = 0x30800000,
				.gicr_base = 0x308c0000,
				.gicc_base = 0x30840000,
				.gich_base = 0x30850000,
				.gicv_base = 0x30860000,
				.maintenance_irq = 25,
			},
		},  
		.root_cell = {
			.name = "e2000d",

			.cpu_set_size = sizeof(config.cpus),
			.num_memory_regions = ARRAY_SIZE(config.mem_regions),
			.num_irqchips = ARRAY_SIZE(config.irqchips),
			.num_pci_devices = ARRAY_SIZE(config.pci_devices),

			.vpci_irq_base = 100,
		},
	},

	.cpus = {
		0x3,
	},

	.mem_regions = {
		/* IVSHMEM shared memory regions */
		{
			.phys_start = 0xa7000000,
			.virt_start = 0xa7000000,
			.size = 0x1000,
			.flags =  JAILHOUSE_MEM_READ,
		},
		{
			.phys_start = 0xa7001000,
			.virt_start = 0xa7001000,
			.size = 0x9000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE,
		},
		{
			.phys_start = 0xa700a000,
			.virt_start = 0xa700a000,
			.size = 0x200000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE,
		},//section0
		{
			.phys_start = 0xa720a000,
			.virt_start = 0xa720a000,
			.size = 0x200000,
			.flags =  JAILHOUSE_MEM_READ,
		},//section1
		{
		    .phys_start = 0xa740a000,
			.virt_start = 0xa740a000,
			.size = 0x200000,
			.flags =  JAILHOUSE_MEM_READ,
		},//seciton2
		
		/* Main memory */
		{
			.phys_start = 0x80000000,
			.virt_start = 0x80000000,
			.size =	      0x80000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_EXECUTE,
		},
		/* Main memory*/ 
		{
			.phys_start = 0x2000000000,
			.virt_start = 0x2000000000,
			.size =	      0x80000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_EXECUTE,
		},
		/* UART 0-3 */
		{
			.phys_start = 0x2800c000,
			.virt_start = 0x2800c000,
			.size = 0x1000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		{
			.phys_start = 0x2800d000,
			.virt_start = 0x2800d000,
			.size = 0x1000,
			.flags =  JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		{
			.phys_start = 0x2800e000,
			.virt_start = 0x2800e000,
			.size = 0x2000, 
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* GPIO 0-5 */
		{
			.phys_start = 0x28034000,
			.virt_start = 0x28034000,
			.size = 0x6000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* I2C 0-1 */
		{
			.phys_start = 0x28020000,
			.virt_start = 0x28020000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		{
			.phys_start = 0x28026000,
			.virt_start = 0x28026000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* Watchdog 0 */
		{
			.phys_start = 0x28040000,
			.virt_start = 0x28040000,
			.size = 0x2000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* Watchdog 1 */
		{
			.phys_start = 0x28042000,
			.virt_start = 0x28042000,
			.size = 0x2000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* IOMMU */
		{
			.phys_start = 0x30000000,
			.virt_start = 0x30000000,
			.size = 0x800000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO,
		},
		/*Usb2 0-4*/
		{
		        .phys_start = 0x31808000,
                        .virt_start = 0x31808000,
                        .size = 0x280000,
            .flags =  JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_IO,
		},
        /*Usb3 0-1*/
        {
                        .phys_start = 0x31a08000,
                        .virt_start = 0x31a08000,
                        .size = 0x30000,
            .flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_IO,
        },
		/*sata 0*/
		{
			.phys_start = 0x31a40000,
                        .virt_start = 0x31a40000,
                        .size = 0x1000,
            .flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_IO,
		},
		/*sata 1*/
        {
                        .phys_start = 0x32014000,
                        .virt_start = 0x32014000,
                        .size = 0x1000,
            .flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
                     JAILHOUSE_MEM_IO,
        },
		/*vpu:no vpu in e2000d dts*/
        /*{
                        .phys_start = 0x32b00000,
                        .virt_start = 0x32b00000,
                        .size = 0x20000,
            .flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
                         JAILHOUSE_MEM_IO,
         },*/
		/* SPI 0-3 */
		{
			.phys_start = 0x2803a000,
			.virt_start = 0x2803a000,
			.size = 0x4000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* QSPI:disable in dts */
		{
			.phys_start = 0x28008000,
			.virt_start = 0x28008000,
			.size = 0x1000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* HDA */
		{
			.phys_start = 0x28006000,
			.virt_start = 0x28006000,
			.size = 0x1000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* CAN 0-2 and SDCI*/
		{
			.phys_start = 0x2800a000,
			.virt_start = 0x2800a000,
			.size = 0x2000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* ETH 0-3 */
		{
			.phys_start = 0x3200c000,
			.virt_start = 0x3200c000,
			.size = 0x8000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* dc */
		{
			.phys_start = 0x32000000,
			.virt_start = 0x32000000,
			.size = 0x8000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* Mailbox */
		{
			.phys_start = 0x32a00000,
			.virt_start = 0x32a00000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO,
		},
		/* sce */
		{
			.phys_start = 0x32a30000,
			.virt_start = 0x32a30000,
			.size = 0x6000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO,
		},
		/* rng */
		{
			.phys_start = 0x32a36000,
			.virt_start = 0x32a36000,
			.size = 0x1000,
			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
				JAILHOUSE_MEM_IO,
		},
		/* SRAM */
		{
			.phys_start = 0x32a10000,
			.virt_start = 0x32a10000,
			.size = 0x2000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* GIC ITS */
		{
			.phys_start = 0x30820000,
			.virt_start = 0x30820000,
			.size = 0x20000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* PCIe ECAM */
		{
			.phys_start = 0x40000000,
			.virt_start = 0x40000000,
			.size = 0x10000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* PCIe IO */
		{
			.phys_start = 0x50000000,
			.virt_start = 0x50000000,
			.size = 0x8000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* PCIe Mem32 */
		{
			.phys_start = 0x58000000,
			.virt_start = 0x58000000,
			.size = 0x28000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
		/* PCIe Mem64 */
		{
			.phys_start = 0x1000000000,
			.virt_start = 0x1000000000,
			.size = 0x1000000000,
			.flags =  JAILHOUSE_MEM_READ |  JAILHOUSE_MEM_WRITE |
				 JAILHOUSE_MEM_IO,
		},
	},

	.irqchips = {
		/* GIC */ 
		{
			.address = 0x30800000,
			.pin_base = 32,
			.pin_bitmap = {
				0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
			},
		},
		{
			.address = 0x30800000,
			.pin_base = 256,
			.pin_bitmap = {
				0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
			},
		},

	},
	
	.pci_devices = {
        	},
	
};
